宇航用处理器发展与展望

年嘉伟; 王旭茹; 刘鸿瑾; 房方; 杨孟飞

doi:10.16383/j.aas.c250393

宇航用处理器发展与展望

doi: 10.16383/j.aas.c250393 cstr: 32138.14.j.aas.c250393

年嘉伟^{1, 2,},
王旭茹^{2, 3,},
刘鸿瑾^{2, 3,},
房方^1,,
杨孟飞⁴

1.
华北电力大学北京 100096
2.
北京轩宇空间科技有限公司北京 100190
3.
北京控制工程研究所北京 100190
4.
中国空间技术研究院北京 100094

基金项目: 空间可信计算与电子信息技术实验室开放基金课题(OBCand-ETL-2025-01(2)), 中央高校面上项目(2025MS028)资助

详细信息

作者简介:
年嘉伟：华北电力大学控制与计算机工程学院讲师. 2018年获得华北电力大学控制与计算机工程学院学士学位, 2024年获得西安电子科技大学计算机科学与技术学院博士学位. 主要研究方向为宇航用处理器架构与容错设计. E-mail: jwnian@ncepu.edu.cn

王旭茹：北京控制工程研究所硕士研究生. 2019年获得西安电子科技大学学士学位. 主要研究方向为宇航用处理器架构与容错设计. 本文通信作者. E-mail: wangxr0321@163.com

刘鸿瑾：北京控制工程研究所研究员. 2008年获得中国科学院研究生院博士学位. 主要研究方向为机载计算机设计, 卫星集成电子系统设计以及基于 SoC 和 SiP 的微电子系统. E-mail: liuhongjin2020@126.com

房方：华北电力大学控制与计算机工程学院教授. 主要研究方向为处理器架构设计, 故障检测. E-mail: ffang@ncepu.edu.cn

杨孟飞：中国科学院院士, 中国空间技术研究院研究员. 主要研究方向为容错设计, 架构设计, 操作系统, 形式化验证和人工智能

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出版历程
- 收稿日期: 2025-08-18
- 录用日期: 2026-01-29
- 网络出版日期: 2026-03-10
- 刊出日期: 2026-08-20

Development and Prospects of Aerospace Processors

NIAN Jia-Wei^{1, 2
,},
WANG Xu-Ru^{2, 3
,},
LIU Hong-Jin^{2, 3
,},
FANG Fang^1
,,
YANG Meng-Fei⁴

1.
North China Electric Power University, Beijing 100096
2.
Bei-jing SunWise Space Technology Co., Ltd., Beijing 100190
3.
Bei-jing Institute of Control Engineering, Beijing 100190
4.
China Academy of Space Technology, Beijing 100094

Funds: Supported by the Open Fund Project of the Space Trustworthy Computing and Electronic Information Technology Laboratory (OBCandETL-2025-01(2)) and the Central University General Project (2025MS028)

More Information

Author Bio:
NIAN Jia-Wei Lecturer at the School of Control and Computer Engineering, North China Electric Power University. He received his bachelor degree from the School of Control and Computer Engineering, North China Electric Power University in 2018, and Ph.D. degree from the School of Computer Science and Technology, Xidian University in 2024. His research interests include aerospace processor architecture and fault-tolerant design

WANG Xu-Ru Master student at the Beijing Institute of Control Engineering. She received her bachelor degree from Xidian University in 2019. Her research interests include aerospace processor architecture and fault-tolerant design. Corresponding author of this paper

LIU Hong-Jin Researcher at the Beijing Institute of Control Engineering. He received his Ph.D. degree from the Graduate University of the Chinese Academy of Sciences in 2008. His research interests include airborne computer design, satellite integrated electronic system design, and microelectronic systems based on SoC and SiP

FANG Fang Professor at the School of Control and Computer Engineering, North China Electric Power University. His research interests include processor architecture design and fault detection

YANG Meng-Fei Academician at the Chinese Academy of Sciences, professor at the China Academy of Space Technology. His research interests include fault-tolerant design, architecture design, operating systems, formal verification, and artificial intelligence

摘要

摘要: 本文系统地回顾了美国、欧洲及我国在宇航用处理器领域的技术演进, 重点分析基于PowerPC架构的美国代表性处理器产品以及采用SPARC架构的欧洲与我国典型处理器方案. 研究揭示, 未来宇航用处理器的发展将显著分化为通用型与智能型两大技术路线. 通用型宇航用处理器将呈现高性能(如提升多核并行计算能力)、高集成度(如实现系统级芯片)、高可靠性(如强化抗辐照设计)及低功耗的协同发展趋势, 而智能型处理器将侧重于提升在轨实时智能信息处理能力.
- 宇航用处理器 /
- 处理器架构 /
- PowerPC /
- SPARC /
- RISC-V
Abstract: This paper provides a systematic review of the technological evolution of aerospace processors in the United States (U.S.), Europe, and China. It primarily analyzes representative U.S. processor products based on the PowerPC architecture, as well as typical European and Chinese processor solutions that utilize the SPARC architecture. The research identifies that the future development of aerospace processors will significantly diverge into two main technical directions: General-purpose and intelligent processors. General-purpose aerospace processors will follow a coordinated trend of increased performance (such as enhanced multi-core parallel computing capabilities), higher integration (such as implementation of system-on-chip designs), improved reliability (such as enhanced radiation-hardened designs), and reduced power consumption. In contrast, intelligent processors will concentrate on advancing real-time intelligent information processing capabilities in-orbit.
- aerospace processor /
- processor architecture /
- PowerPC /
- SPARC /
- RISC-V

HTML全文

图 1 RAD750 架构

Fig. 1 Architecture of RAD750

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图 2 RAD5545 架构

Fig. 2 Architecture of RAD5545

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图 3 TSC695F 架构

Fig. 3 Architecture of TSC695F

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图 4 AT697F 架构

Fig. 4 Architecture of AT697F

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图 5 GR740 架构

Fig. 5 Architecture of GR740

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图 6 NOEL-V 架构

Fig. 6 Architecture of NOEL-V

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图 7 SoC2008 架构

Fig. 7 Architecture of SoC2008

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图 8 SoC2012 架构

Fig. 8 Architecture of SoC2012

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图 9 BM3803FMGRH 架构

Fig. 9 Architecture of BM3803FMGRH

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图 10 美国、欧洲以及我国宇航用处理器发展历程

Fig. 10 The development history of aerospace processors in the U.S., Europe and China

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表 1 美国宇航用处理器各指标对比

Table 1 Comparison of various indicators of U.S. aerospace processors

处理器	架构	内核	主频(MHz)	核心数量	位数	TID (rad (Si))	SEU (错误/(位·天))	SEL (MeV·cm²/mg)	性能	功耗 (W)
RAD6000	PowerPC	RS-6000	33	1	32	—	$ \leq 7.4\times 10^{-10}$	—	35 MIPS	—
RAD750	PowerPC	750	132 ~ 233	1	32	1 M	$ \leq 1.6\times 10^{-10}$	—	200 ~ 400 MIPS	5.0
RAD5510	Power	e5500	466	1	64	1 M	$ \leq 8.0\times 10^{-14} $	—	1.4 GOPS	11.5
RAD5545	Power	e5500	466	4	64	1 M	$\leq 2.0\times 10^{-9}$	—	4.6 GOPS	17.7

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表 2 欧洲宇航用处理器各指标对比

Table 2 Comparison of various indicators of European aerospace processors

处理器	架构	主频 (MHz)	内核	核心数量	流水线	位数	性能 (DMIPS/MHz)	TID (rad (Si))	SEU (错误/(器件·天))	SEL (MeV·cm²/mg)	功耗 (W)	工艺 (nm)
MA31750	—	25	—	1	—	—	—	$ \geq 300\;{\mathrm{K}} $	$ \leq 6\times 10^{-7} $	—	—	—
TSC695F	SPARC V7	25	ERC32	1	四	32	0.80	$ \geq 300\;{\mathrm{K}} $	$ \leq 3\times 10^{-8} $	$ \geq 100 $	$ \leq 1.5 $	500 (MG2RT)
AT697F	SPARC V8	100	LEON2	1	五	32	0.86	$ \geq 300\;{\mathrm{K}} $	$ \leq 1\times 10^{-5} $	$ \geq 70 $	$ \leq 1.0 $	180 (CMOS)
GR740	SPARC V8	250	LEON4-FT	4	七	32	1.70	$ \geq 300\;{\mathrm{K}} $	$ \leq 1\times 10^{-5} $	$ \geq 125 $	$\leq 1.8 $	65 (CMOS)
NOEL-V	RISC-V	—	—	4	七	64	—	—	—	—	—	—

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表 3 龙芯系列产品架构指标

Table 3 Loongson series product architecture indicators

处理器	架构	L1 Cache	L2 Cache	核心数量	主频(Hz)	内存接口	SpaceWire	MIL-STD-1553B	PCI	UART	$ \text{I}^{2}\text{C} $	SPI
1J	MIPS	—	—	1	10 M	—	—	—	—	√	√	√
1F04	MIPS	—	—	1	33 M	SRAM	—	√	√	√	—	—
1F300	MIPS	—	—	1	100 M	SRAM、SDRAM	√	√	√	√	—	—
1E03	MIPS	8 K + 8 K	—	1	100 M	SDRAM	—	—	√	√	√	√
1E300	MIPS	16 K + 16 K	—	1	200 M	SDRAM	—	—	√	√	√	√
1E1000	MIPS	32 K + 32 K	1 M	2	1 G	DDR2/3	√	—	—	√	√	√

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表 4 我国宇航用处理器各指标对比

Table 4 Comparison of various indicators of China＇s aerospace processors

处理器	架构	主频 (MHz)	核心数量	流水线	性能 (DMIPS/MHz)	TID (rad (Si))	SEU (错误/ (器件·天))	SEL (MeV·cm²/mg)	功耗(W)	工艺(nm)
SoC2008	SPARC V8	100	1	七	0.86	$ \geq $ 100 K	$ \leq 1.0\times 10^{-7} $	$ \geq $ 100	$ \leq $ 0.7	130 (CMOS)
SoC2012	SPARC V8	100	4	七	3.00	$ \geq $ 200 K	$ \leq 3.0\times 10^{-8} $	$ \geq $ 100	$ \leq $ 1.0	130 (CMOS)
BM3803FMGRH	SPARC V8	100	1	七	0.85	$ \geq $ 100 K	$ \leq 8.0\times 10^{-5} $	$ \geq $ 75	$ \leq $ 1.0	—
LS1E	MIPS	200	1	—	—	$ \geq $ 300 K	$ \leq 6.5\times 10^{-5 }$	$ \geq $ 75	$ \leq $ 3.0	180 (CMOS)
LS1F	MIPS	100	1	—	—	$ \geq $ 100 K	$ \leq 1.0\times 10^{-5} $	$ \geq $ 75	$ \leq $ 3.0	180 (CMOS)

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