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摘要: 本文根据元胞自动机模型划分方法, 将二维图像分解为2×2矩阵单元结构. 提出了几种逻辑运算式, 用以分类由黑白二值点构成的2×2矩阵图形. 通过CNN神经网络的多层结构形式, 分析了金字塔结构逻辑在相似的组合形式下, 对二值图形边缘检测和池化的功能. 通过同步脉冲形式能将灰度图像, 分解为多个时间维度的二值图形, 方便多层金字塔逻辑运算处理. 分析了如何采用延时继电器使金字塔结构逻辑具有记忆的特性. 讨论了3×3输入金字塔模型, 在不规律脉冲情况下, 通过逻辑运算对线性交点检测的可能.Abstract: In this paper, two-dimensional image is decomposed into 2×2 matrix unit structure according to the method of cellular automata model partition. Several logic operations are proposed to classify 2×2 matrix graphs composed of black and white binary points. The functions of edge processing and pooling of binary graphics in the similar combination form of pyramid structure logic are analyzed through the multi-layer structure form of CNN neural network. The gray scale image can be decomposed into binary graphics with multiple time dimensions by synchronous pulse form, which is convenient for multi-layer pyramid logic operation. This paper analyses how to use delay relay to make pyramid structure logic have the characteristics of memory. This paper discusses the possibility of detecting linear intersection points by logic operation under irregular impulses based on the 3×3 input pyramid model.
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Key words:
- Cellular automata /
- pyramid structure /
- Boolean logic /
- impulse /
- delay relay
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图 1 二值点构成的2×2矩阵所有组合图
Fig. 1 All combination graphs of 2×2 matrix constituted by binary points
图 4 不同特性金字塔逻辑对四边形面不同特征运算图
Fig. 4 Pyramid logic operational diagrams of different characteristics for quadrilateral surfaces
图 3 黑白二值点构成的四边形面输入图
Fig. 3 Quadrilateral input diagram composed of black and white binary points
图 7 金字塔结构逻辑多层阵列对四边形处理图
Fig. 7 Pyramid structural logic multilayer array for quadrilateral processing graph
图 9 金字塔结构逻辑相连构成的组合金字塔图
Fig. 9 Composite pyramid diagram with logically connected pyramid structures
图 10 灰度线AD上各点在50 ms内发放的脉冲数量图
Fig. 10 The number of pulses emitted by each point on the gray line AD in 50 ms
图 11 灰度线AD激活的多层三角结构逻辑运算图
Fig. 11 Gray line AD activated multilayer triangular structure logic operational graph
图 13 不同脉冲次数下生成的二值阵列图
Fig. 13 Binary array diagram generated at different pulse numbers
图 14 逻辑Y在延时脉冲输入情况下的脉冲输出图
Fig. 14 Pulse output diagram of logic Y in the case of delayed pulse input
图 15 逻辑Y在不规律的延时脉冲输入情况下的脉冲输出图
Fig. 15 Logic Y pulse output diagram with irregular delay pulse input
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