Abstract: This paper presents an efficient method of equivalient workstations for modeling and analysis of multistage transfer lines with unreliable machines and finites buffers. The deterministic processing times for discrete parts and random failuse and repair times for machines are assumed. These buffers lead to blockage and starvation in operation due to limited storage capacities and make the problem of modelling and analysis very difficult to treat because they have large state spaces and cannot be decomposed exactly. A single buffer between two reliable workstations is analysed first. Then an equivalent workstation without starvation and blockage is constructed. Thereafter connecting all the equivalent workstations in series we get the equivalent transfer line. A set of preformance measures such as the production rates, efficiencies and average inventory levels are derived in explicit analytical expressions. Finally two numerical examples are given for comparing these calculated results with those of S. B. Gershwin (1987)[3] and C. R. Glasseye & Y. Hong (1993)[5] and illustrating the application of the method in engineering design directly.